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 Zhen Mu, senior principal product engineer with Rayming Design Systems, and Brad Griffin, product marketing director for Cadence, discuss Zhen’s new white paper, “Power-Aware Analysis Solution.” 
Andy Shaughnessy: I'm here at DesignCon 2017 speaking with Zhen Mu from Rayming Design Systems. Zhen is the senior principal product engineer for Cadence, and Zhen I understand you recently published a white paper on a complete power-aware PCB analysis solution. Why don't you tell us about it?
Zhen Mu: Basically, what we want the PCB design community to understand is that the rule checking flow in the PCB design world has been followed for many years, and Rayming has been the leader of the constraint driven flow for over 20 years. For example, you have design goal set up, you explore the design space, then you define constraints. After that, you go ahead to the layout, following the constraints, and after that you run rule checking and do simulations for signoff. Then you get your board out.
Zhen Mu Cadence resized.jpgEverybody is using this flow. One of the questions every PCB designer should be asking is if this flow is complete enough to cover all of the potential design problems. Is this flow still valid? Think about it. Specifically, with high-speed parallel bus designs today, problems are not only tied to signal but also to power. Power noise is becoming more and more important, because the budget has become smaller and smaller. The second question PCB designers should be asking is if the design flow is checking for power noise. Are there any rules to do that? If you're examining your rule set, you probably won't find any.
We want to point out that, when we set up the constraints, we don't even have any physical design, right? The stack-up may have been set up, but we typically don't have much more detail about the physical design. So, the rules, for example, the impedance rules, the coupling rules, are all created in a very ideal environment. There is no power effect at all. Later on, when you do the rule checking on the physical design with the PDN, what do you do? Without any new rule checking technology, design teams still apply the same rule set and simply assume that the PDN did not have any impact on the constraints. For example, when you check signal crosstalk, you still assume that trace reference plane is ideal and the only noise is from other signals, not from anything else.
However, when you have the final design, the plane is there, and the power can bounce because via noise passing through the plane canvas, and then it can destroy all the assumptions associated with the initial constraint. So now if you think about it, when you do the checking at the verification stage, the rule checking or constraint checking, they don't seem to be sophisticated enough for modern PCB designs. You miss all this power and power-induced noise. You have no rules to check for it. It looks like the flow we have been using is running out of steam. That is why we created this white paper. We want to emphasize that we need a new flow, we need new rules, and we need new checking methodologies. This is another important point the white paper tries to address: power-aware checking for the physical design phase.
When talking about new rules to check power noise, we know it is not practical at the early design stage because we do not have any planes yet. So, the flow needs to be enhanced towards the middle or the end of design. At this stage, however, it's harder to do simple rule checking when the plane is bouncing. We have to look at the signal and power noise interactions. Now we found we are moving toward simultaneous switching noise (SSN) analysis, but we don’t want put that level of sophistication into a rule checking flow, it is just too complicated.
Now, we can see that we need a new methodology. Fortunately, we can enable that new methodology using Cadence Sigrity technology. The idea is to compromise a little between simple rule checking and complex SSN analysis. When we are at the stage that a design has the planes and the signals all routed, we can apply a fast, simple simulation to screen the board and find signal and power coupling issues. It is simulation-based, but is a lot faster than a detailed SSN analysis methodology. More importantly, it does not require any complex models—we all know PCB designers do not like dealing with models. Based on the results of the new “power-aware” screening, analysis experts can expedite the advanced analysis and will have fewer problems to clean up as they perform the advanced simulation for signoff.
The new flow that we are proposing is that you still have constraints created at the beginning of the design cycle, but you implement a more detailed screening in the middle of the design and towards the end. The new screening captures problems of signal and the power interactions, and gives designers the chance to fix them much earlier in the design phase. I want to emphasi
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